View AD9430_8391131.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD9430 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 12-bit, 170 msps 3.3 v a/d converter functional block diagram track- and-hold scalable reference adc 12-bit pipeline core lv d s outputs clock management sense vref a gnd drgnd drvdd av d d data, o verrange in lvds or 2-port cmos dco s5 s4 s2 s1 clk+ ds+ vin+ AD9430 12 vin ds clk dco+ select cmos or lvds cmos outputs features snr = 65 db @ f in up to 70 mhz @ 170 msps enob of 10.6 @ f in up to 70 mhz @ 170 msps (C.5 dbfs) sfdr = C80 dbc @ f in up to 70 mhz @ 170 msps (C.5 dbfs) excellent linearity: dnl = 0.3 lsb (typical) inl = 0.5 lsb (typical) two output data options: demultiplexed 3.3 v cmos outputs each @ 85 msps interleaved or parallel data output option lvds at 170 msps 700 mhz full power analog bandwidth on-chip reference and track-and-hold power dissipation = 1.1 w typical @ 170 msps 1.5 v input voltage range 3.3 v supply operation output data format option data sync input and data clock output provided clock duty cycle stabilizer applications wireless and wired broadband communications cable reverse path communications test equipment radar and satellite subsystems power amplifier linearization product description the AD9430 is a 12-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. the product operates up to a 210 msps conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. all necessary functions, including a track-and-hold (t/h) and reference are included on the chip to provide a complete conversion solution. the adc requires a 3.3 v power supply and a differential encode clock for full performance operation. the digital outputs are ttl/cmos or lvds compatible and support either two? complement or offset binary format. separate output power supply pins support interfacing with 3.3 v or 2.5 v cmos logic. two output buses support demultiplexed data up to 105 msps rates in cmos mode. a data sync input is supported for proper output data port alignment in cmos mode and a data clock output is available for proper output data timing. in lvds mode, the chip provides data at the encode clock rate fabricated on an advanced bicmos process, the AD9430 is available in a 100-lead surface-mount plastic package (100 e-pad tqfp) specified over the industrial temperature range (?0 c to +85 c). product highlights 1. high performance?aintains 66 db snr @ 170 msps with a 65 mhz input. 2. low power?onsumes only 1.1 w @ 170 msps 3. ease of use?vds output data and output clock signal allow interface to current fpga techn ology. the on-chip reference a nd sample/hold provide flexibility in system design. use of single 3.3 v supply simplifies system power supply design. 4. out of range (or)?he or output bit indicates when the input signal is beyond the selected input range.
rev. 0 ?2? AD9430especifications dc specifications AD9430bsv-170 parameter temp test level min typ max unit resolution 12 bits accuracy no missing codes full vi guaranteed offset error 25 ci e3 +3 mv gain error 25 ci e5 +5 % fs differential nonlinearity (dnl) 25 ci e 1 0.3 +1 lsb full vi e1 0.3 +1.5 lsb integral nonlinearity (inl) 25 ci e1.5 0.5 +1.5 lsb full vi e1.5 0.5 +2.25 lsb temperature drift offset error full v 58 v/ c gain error full v 0.02 %/ c reference out (vref) full v +0.12/e0.24 mv/ c reference reference out (vref) 25 ci 1.15 1.235 1.3 v output current 1 25 civ 3.0 ma i vref input current 2 25 ci 20 a i sense input current 2 25 ci 1.6 5.0 ma analog inputs (vin+, vine) 3 differential input voltage range (s5 = gnd) full v 1.536 v differential input voltage range (s5 = avdd) full v 0.766 v input common-mode voltage full vi 2.65 2.8 2.9 v input resistance full vi 2.2 3 3.3 k input capacitance 25 cv 5 pf power supply (lvds mode) avdd full iv 3.1 3.3 3.5 v drvdd full iv 3.0 3.3 3.6 v supply currents i analog (avdd = 3.3 v) 4 full vi 335 372 ma i digital (drvdd = 3.3 v) 4 full vi 55 62 ma power dissipation 4 full vi 1.29 1.43 w power supply rejection 25 cv e7.5 mv/v power supply (cmos mode) avdd full iv 3.1 3.3 3.5 v drvdd full iv 3.0 3.3 3.6 v supply currents i analog (avdd = 3.3 v) 5 full iv 335 372 ma i digital (drvdd = 3.3 v) 5 full iv 24 30 ma power dissipation 5 full iv 1.1 w power supply rejection 25 cv e7.5 mv/v notes 1 internal reference mode; sense = floats. 2 external reference mode; sense = drvdd, vref driven by external 1.23 v reference. 3 s5 (pin 1) = gnd. see analog input section. 4 i avdd a nd i drvdd are measured with an analog input of 10.3 mhz, e0.5 dbfs, sine wave, rated encode rate, and in lvds output mode. see typical performance characteristics and applications sections for i drvdd . power consumption is measured with a dc input at rated encode rate in lvds output mode. 5 i avdd and i drvdd are measured with an analog input of 10.3 mhz, e0.5 dbfs, sine wave, rated encode rate, and in cmos output mode. see typical performance characteristics and applications sections for i drvdd . power consumption is measured with a dc input at rated encode rate in cmos output mode. specifications subject to change without notice. (avdd = 3.3 v, drvdd = 3.3 v; t min = e40 c, t max = +85 c, f in = e0.5 dbfs, internal reference, lvds output mode, unless otherwise noted.)
rev. 0 ?3? AD9430 ac specifications 1 AD9430bsv-170 parameter (conditions) temp test level min typ max unit snr analog input @ e0.5 dbfs 10 mhz 25 ci 63 65 db 70 mhz 25 ci 62.5 65 db 100 mhz 25 cv 65 db 240 mhz 25 cv 61 db sinad analog input @ e0.5 dbfs 10 mhz 25 ci 62.5 65 db 70 mhz 25 ci 62 65 db 100 mhz 25 cv 65 db 240 mhz 25 cv 60 db effective number of bits (enob) 10 mhz 25 ci 10.2 10.6 bits 70 mhz 25 ci 10.2 10.6 bits 100 mhz 25 cv 10.6 bits 240 mhz 25 cv 9.8 bits worst harmonic (2nd or 3rd) analog input @ e0.5 dbfs 10 mhz 25 ci e85 e73 dbc 70 mhz 25 ci e80 e72 dbc 100 mhz 25 cv e77 dbc 240 mhz 25 cv e63 dbc worst harmonic (4th or higher) analog input @ e0.5 dbfs 10 mhz 25 ci e87 e76 dbc 70 mhz 25 ci e87 e75 dbc 100 mhz 25 cv e77 dbc 240 mhz 25 cv e63 dbc two-tone imd 2 f1, f2 @ e7 dbfs 25 cv e75 dbc a nalog input bandwidth 25 cv 700 mhz notes 1 all ac specifications tested by driving clk+ and clke differentially. 2 f1 = 28.3 mhz, f2 = 29.3 mhz. specifications subject to change without notice. (avdd = 3.3 v, drvdd = 3.3 v; t min = e40 c, t max = +85 c, f in = e0.5 dbfs, internal reference, lvds output mode, unless otherwise noted.)
rev. 0 AD9430 ?4? switching specifications AD9430bsv-170 parameter (conditions) temp test level min typ max unit maximum conversion rate 1 full vi 170 msps minimum conversion rate 1 full v 40 msps clk+ pulsewidth high (t eh ) 1 full iv 2 12.5 ns clk+ pulsewidth low (t el ) 1 full iv 2 12.5 ns ds input setup time (t sds ) 2 full iv e0.5 ns ds input hold time (t hds ) 2 full iv 1.75 ns output (demux mode) valid time (t v ) full iv 2 ns propagation delay (t pd ) full iv 3.8 5 ns rise time (t r ) (20% to 80%) 25 cv 1 ns fall time (t f ) (20% to 80%) 25 cv 1 ns dco propagation delay (t cpd ) full iv 3.8 5 ns data to dco skew (t pd e t cpd ) full iv e0.5 0 +0.5 ns interleaved mode (a, b latency) full iv 14, 14 cycles parallel mode (a, b latency) full iv 15, 14 cycles output (lvds mode) valid time (t v ) full vi 2.0 ns propagation delay (t pd ) full vi 3.2 4.3 ns rise time (t r ) (20% to 80%) 25 cv 0.5 ns fall time (t f ) (20% to 80%) 25 cv 0.5 ns dco propagation delay (t cpd ) full vi 1.8 2.7 3.8 ns data to dco skew (t pd e t cpd ) full iv 0.2 0.5 0.8 ns pipeline latency full iv 14 cycles a perture delay (t a )25 cv 1.2 ns a perture uncertainty (jitter, t j )25 cv 0.25 ps rms notes 1 all ac specifications tested by driving clk+ and clke differentially. 2 ds inputs used in cmos mode only. specifications subject to change without notice. (avdd = 3.3 v, drvdd = 3.3 v; t min = e40 c, t max = +85 c, unless otherwise noted.) digital specifications AD9430bsv-170 parameter temp test level min typ max unit encode and ds inputs (clk+, clke, ds+, dse) 1 differential input voltage 2 full iv 0.2 v common-mode voltage 3 full vi 1.375 1.5 1.575 v input resistance full vi 3.2 5.5 6.5 k input capacitance 25 cv 4 pf logic inputs (s1, s2, s4, s5) logic 1 voltage full iv 2.0 v logic 0 voltage full iv 0.8 v logic 1 input current full vi 190 a logic 0 input current full vi 10 a input resistance 25 cv 30 k input capacitance 25 cv 4 pf logic outputs (cmos mode) logic 1 voltage 4 full iv drvdd e 0.05 v logic 0 voltage 4 full iv 0.05 v logic outputs (lvds mode) 4, 5 v od differential output voltage full vi 247 454 mv v os output offset voltage full vi 1.125 1.375 v output coding two?s complement or binary notes 1 encode and ds inputs identical on chip. see equivalent circuits section. 2 all ac specifications tested by driving clk+ and clke differentially, |(clk+) e (clke) | > 200 mv. 3 encode inputs common mode can be externally set, such that 0.9 v < enc < 2.6 v. 4 digital output logic levels: drvdd = 3.3 v, c load = 5 pf. 5 lvds r term = 100 , lvds output current set resistor = 3.74 k (1% tolerance). specifications subject to change without notice. (avdd = 3.3 v, drvdd = 3.3 v; t min = e40 c, t max = +85 c, unless otherwise noted.)
rev. 0 AD9430 ?5? n-14 n-13 n n+1 a in clk+ clke data out dco+ dcoe n n+1 ne1 t eh t el 1/f s t pd 14 cycles t cpd figure 1. lvds timing diagram port a d7ed0 port b d7ed0 p arallel data out port a d7ed0 port b d7ed0 dco+ dcoe clk+ clke ds+ dse interleaved data out static static static static static invalid invalid invalid invalid invalid invalid invalid t sds 14 cycles t pd t v n n+2 n+3 n+1 n n+2 n+1 n+3 t cpd t hds figure 2. cmos timing diagram
rev. 0 AD9430 ?6? absolute maximum ratings 1 avdd, drvdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 v analog inputs . . . . . . . . . . . . . . . . . e0.5 v to avdd + 0.5 v digital inputs . . . . . . . . . . . . . . . . e0.5 v to drvdd + 0.5 v refin inputs . . . . . . . . . . . . . . . . . e0.5 v to avdd + 0.5 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature . . . . . . . . . . . . . . . . . e55c to +125 c storage temperature . . . . . . . . . . . . . . . . . . . e65c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . . 150 c maximum case temperature . . . . . . . . . . . . . . . . . . . . 150 c ja 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 c/w, 32 c/w 1 s tresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. 2 typical ja = 32 c/w (heat slug not soldered), typical ja = 25 c/w (heat slug soldered), for multilayer board in still air with solid ground plane. explanation of test levels test level i. 100% production tested. ii. 100% production tested at 25 c and sample tested at specified temperatures. iii. sample tested only. iv. parameter is guaranteed by design and characterization testing. v. parameter is a typical value only. vi. 100% production tested at 25 c; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9430 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide temperature package model range option AD9430bsv-170 e40 c to +85 c tqfpe100 AD9430/pcb-lvds 25 ce valuation board (lvds mode) AD9430/pcb-cmos 25 ce valuation board (cmos mode)
rev. 0 AD9430 C7C pin function descriptions (cmos mode) pin number pin name function 1s5 full-scale adjust pin; avdd sets f s = 0.768 v p-p differential gnd sets f s = 1.536 v p-p differential 2, 7, 42, 43, 65, 66, 68 dnc do not connect 3s 4 interleaved, parallel select pin. high = interleaved . 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, agnd analog ground 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100 5s 2o utput mode select. low = dual-port cmos; high = lvds. 6s 1d ata format select. low = binary, high = two? complement. 8, 14, 15, 18, 19, 24, 27, 28, 29, 34, 39, 40, avdd 3.3 v analog supply 88, 89, 90, 94, 95, 98, 99 10 sense reference mode select pin 11 vref 1.235 reference i/o ?function dependent on sense 21 vin+ analog input ?true 22 vin analog input ?complement 32 ds+ data sync (input) ?true. tie low if not used. see timing diagram. 33 ds data sync (input) ?complement. tie high if not used. 36 clk+ clock input ?true 37 clk c lock input ?complement 44 db0 b port output data bit (lsb) 45 db1 b port output data bit 46 db2 b port output data bit 47, 54, 62, 75, 83 drvdd 3.3 v digital output supply (3.0 v 3.6 v) 48, 53, 61, 67, 74, 82 drgnd digital output ground 49 db3 b port output data bit 50 db4 b port output data bit 51 db5 b port output data bit 52 db6 b port output data bit 55 db7 b port output data bit 56 db8 b port output data bit 57 db9 b port output data bit 58 db10 b port output data bit 59 db11 b port output data bit (msb) 60 or_b b port overrange 63 dco d ata clock output ?complement 64 dco+ d ata clock output ?true 69 da0 a port output data bit (lsb) 70 da1 a port output data bit 71 da2 a port output data bit 72 da3 a port output data bit 73 da4 a port output data bit 76 da5 a port output data bit 77 da6 a port output data bit 78 da7 a port output data bit 79 da8 a port output data bit 80 da9 a port output data bit 81 da10 a port output data bit 84 da11 a port output data bit (msb) 85 or_a a port overrange note agnd and drgnd should be tied together to common ground plane.
rev. 0 AD9430 ?8? pin function descriptions (lvds mode) pin number pin name function 1s5 full-scale adjust pin; avdd sets f s = 0.768 v p-p differen tial gnd sets f s = 1.536 v p-p differential 2, 42e46 dnc do not connect 3s 4c ontrol pin for cmos mode, tie low when operating in lvds mode. 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, agnd analog ground 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100 5s 2 output mode select. gnd = dual-port cmos; avdd = lvds. 6s 1d ata format select. gnd = binary; avdd = two?s complement. 7 lvdsbias set pin for lvds output current. place 3.7 k resistor terminated to ground. 8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34, 39, avdd 3.3 v analog supply 40, 88, 89, 90, 94, 95, 98, 99 10 sense control pin for reference, full scale 11 vref 1.235 reference i/o e function dependent on sense 21 vin+ analog input e true 22 vine analog input e complement 32 gn d data sync (input) e not used in lvds mode. tie to gnd. 36 clk+ clock input e true (lvpecl levels) 37 clke clock input e complement (lvpecl levels) 47, 54, 62, 75, 83 drvdd 3.3 v digital output supply (3.0 v e 3.6 v) 48, 53, 61, 67, 74, 82 drgnd digital output ground 49 d0e d0 complement output bit (lsb) 50 d0+ d0 true output bit (lsb) 51 d1e d1 complement output bit 52 d1+ d1 true output bit 55 d2e d2 complement output bit 56 d2+ d2 true output bit 57 d3e d3 complement output bit 58 d3+ d3 true output bit 59 d4e d4 complement output bit 60 d4+ d4 true output bit 63 dcoe data clock output e complement 64 dco+ data clock output e true 65 d5e d5 complement output bit 66 d5+ d5 true output bit 68 d6e d6 complement output bit 69 d6+ d6 true output bit 70 d7e d7 complement output bit 71 d7+ d7 true output bit 72 d8e d8 complement output bit 73 d8+ d8 true output bit 76 d9e d9 complement output bit 77 d9+ d9 true output bit 78 d10e d10 complement output bit 79 d10+ d10 true output bit 80 d11e d11 complement output bit 81 d11+ d11 true output bit 84 ore overrange complement output bit 85 or+ overrange true output bit
rev. 0 AD9430 ?9? pin configurations 26 27 28 29 30 55 54 53 52 51 cmos pinout top view (not to scale) AD9430 agnd avdd avdd avdd agnd 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 25 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 31 37 agnd ds+ dse avdd agnd clk+ clke agnd avdd avdd agnd dnc dnc db0 db1 db2 drvdd drgnd db3 db4 80 da9 79 da8 78 da7 77 da6 76 da5 75 drvdd 74 drgnd 73 da4 72 da3 71 da2 70 da1 69 da0 68 dnc 67 drgnd 66 dnc 65 dnc 64 dco+ 63 dcoe 62 drvdd 61 drgnd 60 or_b 59 db11 58 db10 57 db9 56 db8 db7 drvdd drgnd db6 db5 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 agnd avdd avdd agnd agnd avdd avdd agnd agnd agnd avdd avdd avdd agnd agnd or_a da11 drvdd drgnd da10 s5 dnc s4 agnd s2 s1 dnc avdd agnd sense vref agnd agnd avdd avdd agnd agnd avdd avdd agnd vin+ vine agnd avdd agnd AD9430 cmos dual-mode pinout 26 27 28 29 30 55 54 53 52 51 lvds pinout top view (not to scale) AD9430 agnd avdd avdd avdd agnd 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 25 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 31 37 agnd gnd avdd avdd agnd clk+ clke agnd avdd avdd agnd dnc dnc dnc dnc dnc drvdd drgnd d0e d0+ 80 d11e 79 d10+ 78 d10e 77 d9+ 76 d9e 75 drvdd 74 drgnd 73 d8+ 72 d8e 71 d7+ 70 d7e 69 d6+ 68 d6e 67 drgnd 66 d5+ 65 d5e 64 dco+ 63 dcoe 62 drvdd 61 drgnd 60 d4+ 59 d4e 58 d3+ 57 d3e 56 d2+ d2e drvdd drgnd d1+ d1e 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 agnd avdd avdd agnd agnd avdd avdd agnd agnd agnd avdd avdd avdd agnd agnd or+ ore drvdd drgnd d11+ s5 dnc s4 agnd s2 s1 lvdsbias avdd agnd sense vref agnd agnd avdd avdd agnd agnd avdd avdd agnd vin+ vine agnd avdd agnd AD9430 lvds mode pinout
rev. 0 AD9430 ?10? definitions analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between the 50% point of the rising edge of the encode co mmand and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. crosstalk coupling onto one channel being driven by a low level (e40 dbfs) signal when the adjacent interfering channel is driven by a full- scale signal. differential analog input resistance, differential analog input capacitance, and differential analog input impedance the real and complex impedances measured at each analog input port. the resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. differential analog input voltage range the peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. peak differential voltage is computed by observing the voltage on a single pin and sub- tracting the voltage from the other pin, which is 180 degrees out of phase. peak-to-peak differential is computed by rotating the inputs phase 180 degrees and again taking the peak measurement. the difference is then computed between both peak measurements. differential nonlinearity the deviation of any code width from an ideal 1 lsb step. effective number of bits the effective number of bits (enob) is calculated from the measured snr based on the equation: enob snr db measured = e. . 176 602 encode pulsewidth/duty cycle pulsewidth high is the minimum amount of time that the encode pulse should be left in logic 1 state to achieve rated performance; pulsewidth low is the minimum time encode pulse should be left in low state. see timing implications of changing t ench in text. at a given clock rate, these specifications define an acceptable encode duty cycle. full-scale input power expressed in dbm. computed using the following equation: power v z fullscale fullscale input rms = 10 0 001 2 log . gain error gain error is the difference between the measured and ideal full- scale input voltage range of the adc. harmonic distortion, second the ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dbc. harmonic distortion, third the ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dbc. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a best straight line determined by a least square curve fit. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate t he encode rate at which parametric testing is performed. output propagation delay the delay between a differential crossing of encode and encode and the time when all output data bits are within valid logic levels. noise (for any range within the adc) vz fs snr signal noise dbm dbc dbfs = 0 001 10 10 . ee where z is the input impedance, fs is the full scale of the device for the frequency in question, snr is the value for the particular input level, and signal is the signal level within the adc reported in db below full scale. this value includes both thermal and quan- tization noise. power supply rejection ratio the ratio of a change in input offset voltage to a change in power supply voltage. signal-to-noise-and-distortion (sinad) the ratio of the rms signal amplitude (set 1 db below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious component may or may not be a harmonic. may be reported in dbc (i.e., degrades as signal level is lowered) or dbfs (always related b ack to con- verter full scale). two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dbc. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. may be reported in dbc (i.e., degrades as signal level is lowered) or in dbfs (always related back to converter full scale).
rev. 0 AD9430 ?11? worst other spur the ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dbc. transient response time transient response is defined as the time it takes for the adc to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. out-of-range recovery time out-of-range recovery time is the time it takes for the adc to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. equivalent circuits clk+ or ds+ 12k 10k 150 150 12k 10k av d d clke or dse figure 3. encode and ds inputs vin+ 3.5k 20k 3.5k 20k av d d vine figure 4. analog inputs s1, s2, s4, s5 vdd 30k figure 5. s1?s5 inputs a1 vref 1k sense 200 0.1 f disable a1 vdd k full scale s5 = 0 ?> k = 1.24 s5 = 1 ?> k = 0.62 e + 1v figure 6. vref, sense i/o dx drvdd figure 7. data outputs (cmos mode) drvdd dxe dx+ v v v v v
rev. 0 AD9430 ?12? mhz 040 85 10 20 30 50 60 70 80 db 0 e100 e10 e20 e80 e30 e40 e50 e60 e70 e90 snr = 65.2db sinad = 65.1db h2 = e88.8dbc h3 = e88.1dbc sfdr = 87dbc tpc 1. fft: f s = 170 msps, a in = 10.3 mhz @ ?0.5 dbfs, lvds mode mhz 040 85 10 20 30 50 60 70 80 db 0 e100 e10 e20 e80 e30 e40 e50 e60 e70 e90 snr = 65.1db sinad = 64.9db fund = e0.50dbfs h2 = e88.6dbc h3 = e94.6dbc sfdr = 85.9dbc tpc 2. fft: f s = 170 msps, a in = 65 mhz @ ?0.5 dbfs, lvds mode mhz 040 85 10 20 30 50 60 70 80 db 0 e100 e10 e20 e80 e30 e40 e50 e60 e70 e90 snr = 64.93db sinad = 64.85db fund = e0.44dbfs h2 = e92.1dbc h3 = e90.1dbc sfdr = 75.6dbc tpc 3. fft: f s = 170 msps, a in = 65 mhz @ ?0.5 dbfs, differential, 1.5 v p-p input range, cmos mode mhz 040 85 10 20 30 50 60 70 80 db 0 e100 e10 e20 e80 e30 e40 e50 e60 e70 e90 snr = 62.99dbfs sinad = 61.45dbfs h2 = e66.8dbc h3 = e82.5dbc sfdr = 66.1dbc tpc 4. fft: f s = 170 msps, a in = 10.3 mhz @ ?0.5 dbfs, single-ended input, 0.76 v input range, lvds mode a in e mhz 0 200 400 50 100 150 250 300 350 db 100 40 90 50 80 70 60 2nd 3rd sfdr tpc 5. harmonic distortion (second and third) and sfdr vs. a in frequency, f s = 170 msps, lvds mode a in e mhz 0 200 400 50 100 150 250 300 350 db 100 40 90 50 80 70 60 2nd 3rd sfdr tpc 6. harmonic distortion (second and third) and sfdr vs. a in frequency, f s = 170 msps, cmos mode et ypical performance characteristics
rev. 0 AD9430 ?13? mhz 040 85 10 20 30 50 60 70 80 db 0 e100 e10 e20 e80 e30 e40 e50 e60 e70 e90 sfdr = 75dbc tpc 7. two-tone intermodulation distortion (28.3 mhz and 29.3 mhz; lvds mode, f s = 170 msps) mhz 0 250 50 100 150 200 db 95 50 90 55 80 75 65 85 70 60 sinad sfdr tpc 8. sinad and sfdr vs. encode rate (a in = 10.3 mhz @ ?0.5 dbfs, lvds mode) analog supply current cmos mode analog supply current lvds mode output supply current lvds mode output supply current cmos mode encode e msps 100 220 140 160 180 200 120 i av d d (analog supply current) e ma 400 0 350 50 250 150 300 200 100 i drvdd (output supply current) e ma 80 60 40 20 10 tpc 9. i avdd and i drvdd vs. encode rate (a in = 10.3 mhz @ ?0.5 dbfs) 170 msps grade, c load = 5 pf sinad snr sfdr encode positive duty cycle e % 10 60 90 20 40 50 70 80 30 db 85 50 80 75 70 65 60 55 tpc 10. sinad and sfdr vs. encode pulsewidth high (a in = 10.3 mhz @ ?0.5 dbfs, 170 msps, lvds) i ref e ma 058 13467 2 v ref e v 1.4 0 1.2 1.0 0.8 0.6 0.4 0.2 r o = 13 typ tpc 11. v refout vs. i load temperature e c e50 10 95 e30 e10 30 50 70 90 gain error e % e2.0 1.5 e1.0 1.0 .5 0 e.5 e1.5 % gain error using ext ref 2.0 tpc 12. full-scale gain error vs. temperature (a in = 10.3 mhz @ ?0.5 dbfs, 170 msps, lvds)
rev. 0 AD9430 ?14? av d d e v 2.5 3.1 4.0 2.7 2.9 3.3 3.5 3.7 3.9 v ref e v 1.250 1.225 1.230 1.245 1.240 1.235 tpc 13. v ref output voltage vs. avdd temperature e c e50 10 95 e30 e10 30 50 70 90 db 95 60 90 70 85 80 75 65 3rd 2nd sfdr snr sinad tpc 14. snr, sinad, sfdr vs. temperature (a in = 10.3 mhz @ ?0.5 dbfs, 170 msps) code 0 4000 500 1500 2500 3000 1000 2000 3500 lsb 1 e1 0.75 e0.75 0.25 e0.25 0.5 0 e0.5 tpc 15. typical inl plot (a in = 10.3 mhz @ ?0.5 dbfs, 170 msps, lvds) code 0 4000 500 1500 2500 3000 1000 2000 3500 lsb 1 e1 0.75 e0.75 0.25 e0.25 0.5 0 e0.5 tpc 16. typical dnl plot (a in = 10.3 mhz @ ?0.5 dbfs, 170 msps, lvds) analog input level e dbfs e100 0 e70 e50 e30 e20 e60 e40 e10 e80 e90 db 100 0 70 10 50 30 60 40 20 80 90 sfdr edbfs sfdr edbc 80db reference line tpc 17. sfdr vs. a in input level 10.3 mhz, a in @ 170 msps, lvds mhz 2.65 42.5 21.25 noise input level e db 0 e140 e40 e120 e100 e60 e80 e20 npr = 56.95db encode = 170msps notch @ 19mhz tpc 18. noise power plot ratio
rev. 0 AD9430 ?15? full-scale range e v 0.000 2.500 2.000 1.000 1.500 0.500 db 90 0 70 10 50 30 60 40 20 80 sinad snr sfdr tpc 19. snr, sinad, sfdr vs. full-scale range temperature e c e40 100 60 20 40 e20 0 80 ns 4.5 2.5 4.0 3.5 3.0 tpd tcpd tpc 20. propagation delay vs. temperature, lvds tcpd (clockout rising) temperature e c e40 100 60 20 40 e20 0 80 ns 4.5 2.5 4.0 3.5 3.0 tpdf (data falling) tpdr (data rising) tpc 21. propagation delay vs. temperature, cmos lv ds output current set resistor reset e k 014 10 68 24 12 v dif e mv 900 0 700 500 300 800 600 400 200 100 1.4 0.5 1.2 1.0 0.8 1.3 1.1 0.9 0.7 0.6 v os e v v os v od tpc 22. lvds output swing, common-mode voltage vs. rset, placed at lvdsbias
rev. 0 AD9430 ?16? application notes theory of operation the AD9430 architecture is optimized for high speed and ease of use. the analog inputs drive an integrated high bandwidth track- and-hold circuit that samples the signal prior to quantization by the 12-bit core. for ease of use, the part includes an onboard reference and input logic that accepts ttl, cmos, or lvpecl levels. the digital outputs logic levels are user selectable as standard 3 v cmos or lvds (ansi-644 compatible) via pin s2. encode input any high speed a/d converter is extremely sensitive to the quality of the sampling clock provided by the user. a track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock will be combined with the desired signal at the a/d output. for that reason, considerable care has been taken in the design of the encode input of the AD9430, and the user is advised to give commensurate thought to the clock source. the AD9430 has an internal clock duty cycle stabilization circuit that locks to the rising edge of encode (falling edge of encode if driven differentially) and optimizes timing internally. this allows for a wide range of input duty cycles at the input without degrading performance. jitter in the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. this circuit is always on and cannot be disabled by the user. the enclock inputs are internally biased to 1.5 v (nominal) and support either differential or single-ended signals. for best dynamic performance, a differential signal is recommended. an mc100lvel16 performs well in the circuit to drive the encode inputs, as illustrated in figure 9. note that for this low voltage pecl device, the ac coupling is optional. pecl gate 510 510 0.1 f 0.1 f clke AD9430 clk+ figure 9. driving encode with lvel16 analog input the analog input to the AD9430 is a differential buffer. for best dynamic performance, impedances at vin+ and vine should match. the analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differen- tially. snr?s and sinad?s performance will degrade significantly if the analog input is driven with a single-ended signal. a wideband transformer, such as minicircuits adt1-1wt, can provide the differential analog inputs for applications that require a single- ended-to-differential conversion. both analog inputs are self-biased by an on-chip resistor divider to a nominal 2.8 v (see equivalent circuits section). special care was taken in the design of the analog input section of the AD9430 to prevent damage and corruption of data when the input is overdriven. the nominal input range is 1.5 v diff p-p. the nominal differential input range is 768 mv p-p 2. table i. output select coding s2 s5 s1 (lvds/cmos s4 (full-scale (data format select) mode select) 1 (i/p select) select) 2 mode 1x xx two?s complement 0x xx offset binary x0 1x dual-mode cmos interleaved x0 0x dual-mode cmos parallel x1xxl vds mode xx x1 full scale = 0.768 v xx x0 full scale = 1.536 v x = don?t care notes 1 s4 used in cmos mode only (s2 = 0). s1es5 all have 30 k resistive pull-downs on chip. 2 s5 full-scale adjust (see analog input section). in interleaved mode, output data on port a is offset from output data changes on port b by one-half output clock cycle: interleaved mode parallel mode
rev. 0 AD9430 ?17? 2.8v 2.8v v in+ v ine 768mv s5 = gnd figure 10. differential analog input range 2.8v s5 = avdd 768mv v in+ v ine = 2.8v 2.8v figure 11. single-ended analog input range digital outputs the off-chip drivers on the chip can be configured to provide cmos- or lvds-compatible output levels via pin s2. the cmos digital outputs (s2 = 0) are ttl /cmos-compatible for lower power consumption. the outputs are biased from a separate supply (drvdd), allowing easy interface to external logic. the outputs are cmos devices that will swing from ground to drvdd (with no dc load). it is recommended to minimize the capacitive load the adc drives by keeping the output traces short (<1 inch, for a total c load < 5 pf). when operating in cmos mode, it is also recommended to place low value (20 ) series damping resistors on the data lines to reduce switching transient effects on performance. lvds outputs lvds outputs are available when s2 = v dd and a 3.4 rset resistor is placed at pin 7 (lvdsbias) to ground. the rset resistor current (~ 1.2/rset) is ratioed on-chip setting the output current at each output equal to a nominal 3.5 ma (10 irset). a 100 differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing at the receiver. lvds mode facilitates interfacing with lvds receivers in custom asics and fpgas that have lvds capability for superior switch- ing performance in noisy environments. single point-to-point net topologies are recommended with a 100 termination resistor as close to the receiver as possible. it is recommended to keep the trace length 1e2 inches and keep differential output trace lengths equal as possible. clock outputs (dco, dco codco dco dco co cod d dd dd cod d od dd d dd c c d dc
rev. 0 AD9430 ?18? AD9430 evaluation board the AD9430 evaluation board offers an easy way to test the AD9430. it requires a clock source, an analog input signal, and a 3.3 v power supply. the clock source is buffered on the board to provide the clocks for the adc, an on-board dac, latches, and a data ready signal. the digital outputs and output clocks are available at two 40-pin connectors, p3 and p4. the board has several different modes of operation and is shipped in the following configuration: ? offset binary ? internal voltage reference ? cmos parallel timing ? full-scale adjust = low power connector power is supplied to the board via a detachable 12-lead power strip (three 4-pin blocks). table ii. power connector avdd 3.3 v analog supply for adc (~ 350 ma) drvdd 3.3 v output supply for adc (~ 28 ma) vdl 3.3 v supply for support logic and dac (~350 ma) ext_vref * optional external reference input vclk/v_xtal supply for clock buffer/optional xtal vamp supply for optional amp * lvel16 clock buffer can be powered from avdd or vclk at e47 jumper (avdd, drvdd, and vdl are the minimum required power connections). analog inputs the evaluation board accepts a 1.3 v p-p analog input signal centered at ground at smb connector j4. this signal is terminated to ground through 50 by r16. the input can be alternatively terminated at t1 transformer secondary by r13 and r14. t1 is a wideband rf transformer providing the single-ended-to-differential con- version, allowing the adc to be driven differentially, minimizing even order harmonics. an optional second transformer, t2, can be placed following t1 if desired. this would provide some per- formance advantage (~1e2 db) for high analog input frequencies (>100 mhz). if t2 is placed, two shorting traces at the pads would need to be cut. the analog signal is low-pass filtered by r41, c12, and r42, c13 at the adc input. gain full scale is set at e17ee19, e17ee18 sets s5 low, full scale = 1.5 v differential; e17ee19 sets s5 high, full scale = 0.75 v differential. encode the encode clock is terminated to ground through 50 at smb connector j5. the input is ac-coupled to a high-speed differen- tial receiver (lvel16) that provides the required low-jitter, fast edge rates needed for optimum performance. j5 input should be > 0.5 v p-p. power to the el16 is set at jumper e47. e47ee45 powers the buffer from avdd, e47ee46 powers the buffer from vclk/v_xtal. voltage reference the AD9430 has an internal 1.23 v voltage reference. the adc uses the internal reference as the default when jumpers e24ee27 and e25ee26 are left open. the full scale can be increased by placing optional resistor r3. the required value would vary with process and needs to be tuned for the specific application. full scale can similarly be reduced by placing r4; tuning would be required here as well. an external reference can be used by shorting the sense pin to 3.3 v (place jumper e26ee25). e27ee24 jumper connects the adc vref pin to ext_vref pin at the power connector. data format select data format select sets the output data format of the adc. setting dfs (e1ee2) low sets the output format to be offset binary; setting dfs high (e1ee3) sets the output to two?s complement. i/p output timing is set at e11ee13. e12ee11 sets s4 low for parallel output timing mode. e11ee13 sets s4 high for interleaved timing mode. timing controls flexibility in latch clocking and output timing is accomplished by allowing for clock inversion at the timing controls section of the pcb. each buffered clock is buffered by an xor and can be inverted by moving the appropriate jumper for that clock. data outputs the adc digital outputs are latched on the board by four lvt574s; the latch outputs are available at the two 40-pin connectors at pins 11e33 on p23 (channel a) and pins 11e33 on p3 (channel b). the latch output clocks (data ready) are available at pin 37 on p23 (channel a) and pin 37 on p3 (channel b). the data ready clocks can be inverted at the timing controls section if needed. ch1 ch2 ch2 m 5.00ns 1 2 : 4.6ns c1 freq 84.65608mhz 2.00v 2.00v figure 13. data output and clock @ 80-pin connector
rev. 0 AD9430 ?19? dac outputs each channel is reconstructed by an on-board dual-channel dac, an ad9753. this dac is intended to assist in debug?it should not be used to measure the performance of the adc. it is a current output dac with on-board 50 termination resis- tors. the figure below is representative of the dac output with a full-scale analog input. the scope setting is low bandwidth. ch1 ch1 m 25.0ns 1 c1 freq 10.33592mhz c1 pk-pk 448mv 2.00mv 248mv figure 14. dac output encode xtal an optional xtal oscillator can be placed on the board to serve as a clock source for the pcb. power to the xtal is through the vclk/vxtal pin at the power connector. if an oscillator is used, ensure proper termination for best results. the board has been tested with a valpey fisher vf561 and a vectron jn00158-163.84. test results for the vf561 are shown below. mhz 0 e30 080 20 db 40 60 e60 e80 e20 e10 e50 e40 e100 e90 e70 encode 163.84mhz analog 65.02mhz snr 63.93db sinad 63.87db fund e0.45dbfs 2nd e85.62dbc 3rd e91.31dbc 4th e90.54dbc 5th e90.56dbc 6th e91.12dbc thd e82.21dbc sfdr 83.93dbc samples 8k noiseflr e100.44dbfs w orstsp e83.93dbc figure 15. fft?using vf561 xtal as clock source optional amplifier the footprint for transformer t2 can be modified to accept a wideband differential amplifier (ad8350) for low-frequency applications where gain is required. note that pin 2 would need to be lifted and left floating for operation. input transformer t1 would need to be modified to a 4:1 for impedance matching and adc input filtering would enhance performance (see ad8350 data sheet). snr/sinad performance of 61 db/60 db is possible and would start to degrade at about 30 mhz. cut trace ad8350 1 cut trace figure 16. using the ad8350 on the AD9430 pcb troubleshooting if the board does not seem to be working correctly, try the following: ? verify power at ic pins. ? check that all jumpers are in the correct position for the desired mode of operation. ? verify vref is at 1.23 v. ? try running encode clock and analog inputs at low speeds (10 msps/1 mhz) and monitor 574, dac, and adc outputs for toggling. the AD9430 evaluation board is provided as a design example for customers of analog devices, inc. adi makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose. signal generator signal generator refin 10mhz refout b and-pass filter analog j4 clock j5 AD9430 evaluation board av d d gnd drvdd gnd vdl gnd 3.3v +e 3.3v +e 3.3v +e data capture and processing figure 17. evaluation board connections
rev. 0 AD9430 ?20? table iii. evaluation board bill of materials no. quantity reference designator device package value comments 14 7c 1, c3ec11, c15ec17, capacitor 0603 0.1 fc43 , c47 c19ec29, c31ec48, c58ec62 not placed 21 c2 capacitor 0603 10 pf not placed 32 c12, c13 capacitor 0603 20 pf not placed 41 c14 capacitor 0603 0.01 f 51 c18 capacitor 0603 1 f 67 c30, c49, c63ec67 capacitor capl 10 fc 30 not placed 79 e3ee1ee2 3-pin header/jumper e19ee17ee18 3-pin header/jumper e13ee11ee12 3-pin header/jumper e26ee25ee27ee24 4-pin header e46ee47ee45 3-pin header/jumper e35ee33ee34 3-pin header/jumper e32ee30ee31 3-pin header/jumper e29ee23ee28 3-pin header/jumper e22ee16ee21 3-pin header/jumper 86 j1, j2, j3, j4, j5, j6 smb smb j2 not placed 92 p3, p23 40-pin header 10 3 p4, p21, p22 4-pin power connector post z5.531.3425.0 wieland detachable connector 25.602.5453.0 wieland 11 10 r1, r5, r13, r14, r16, resistor 0603 50 r1, r13, r14 r25, r27, r28, r41, r42 not placed 12 3 r2, r3, r4 resistor 0603 3.9 k r3, r4 not placed 13 14 r6er8, r10, r15, r21er24, resistor 0603 100 r15, r21er24, r33er36, r38 not placed 14 5 r9, r11, r12, r30, r37 resistor 0603 0 15 4 r17, r18, r19, r20 resistor 0603 510 16 1 r26 resistor 0603 2 k 17 1 r29 resistor 0603 390 18 7 r31, r32, r39, r40, r43, resistor 0603 1 k r44, r45 19 4 rz1, rz2, rz3, rz4 resistor pack 220 so16res 742c163221jtr cts 20 8 rz5, rz6, rz7, rz8, resistor pack 22 so16res 742c163220jtr cts rz9, rz10, rz11, rz12 21 2 t1, t2 transformer cd542 minicircuits t2 not placed adt1e1wt 22 1 u1 AD9430bsv tqfp100 adc 23 1 u2 mc100lvel16d so8nb clock buffer 24 1 u3 74lvc86 so14nb xor 25 4 u4, u5, u6, u7 74lvt574 so20 latch 26 1 u9 ad9753ast lqfp48 dac
rev. 0 AD9430 ?21? vcc vee dq dn qn vbb gnd e45 e46 vcc vclk e47 c36 0.1 f j5 gnd r27 50 c5 0.1 f encode 2 3 4 5 6 7 8 c8 0.1 f r10 510 r17 510 mc100lvel 16 u2 gnd r20 510 r19 510 gnd out_en d0 d1 d2 d3 d4 d5 d6 d7 gnd vcc q0 q1 q2 q3 q4 q5 q6 q7 clock l vt574 u7 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 clklatb vdl gnd gnd r1 r2 r3 r4 r5 r6 r7 r8 rz5 22 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 dy 4 dy 3 dy 2 dy 1 dy 0 dya dy b r1 r2 r3 r4 r5 r6 r7 r8 rz4 220 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 out_en d0 d1 d2 d3 d4 d5 d6 d7 gnd vcc q0 q1 q2 q3 q4 q5 q6 q7 clock l vt574 u6 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 clklata vdl gnd gnd r1 r2 r3 r4 r5 r6 r7 r8 rz6 22 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 dry dy 1 1 dy 1 0 dy 9 dy 8 dy 7 dy 6 dy 5 r1 r2 r3 r4 r5 r6 r7 r8 rz3 220 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c4oms p3 p40 p38 p36 p34 p32 p30 p28 p26 p24 p22 p20 p18 p16 p14 p12 p10 p8 p6 p4 p2 p39 p37 p35 p33 p31 p29 p27 p25 p23 p21 p19 p17 p15 p13 p11 p9 p7 p5 p3 p1 gnd drb gnd dy 1 1 dy 1 0 dy 9 dy 8 dy 7 dy 6 dy 5 dy 4 dy 3 dy 2 dy 1 dy 0 dya dy b dry gnd gnd out_en d0 d1 d2 d3 d4 d5 d6 d7 gnd vcc q0 q1 q2 q3 q4 q5 q6 q7 clock l vt574 u4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 dm8 dm7 dm6 dm5 clklata vdl gnd gnd r1 r2 r3 r4 r5 r6 r7 r8 rz8 22 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 drx dx11 dx10 dx9 dx8 dx7 dx6 dx5 r1 r2 r3 r4 r5 r6 r7 r8 rz1 220 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c4oms p23 p40 p38 p36 p34 p32 p30 p28 p26 p24 p22 p20 p18 p16 p14 p12 p10 p8 p6 p4 p2 p39 p37 p35 p33 p31 p29 p27 p25 p23 p21 p19 p17 p15 p13 p11 p9 p7 p5 p3 p1 gnd dra gnd dx11 dx10 dx9 dx8 dx7 dx6 dx5 dx4 dx3 dx2 dx1 dx0 dxa dxb drx gnd gnd out_en d0 d1 d2 d3 d4 d5 d6 d7 gnd vcc q0 q1 q2 q3 q4 q5 q6 q7 clock l vt574 u5 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 clklata vdl gnd gnd r1 r2 r3 r4 r5 r6 r7 r8 rz7 22 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 dx4 dx3 dx2 dx1 dx0 dxa dxb r1 r2 r3 r4 r5 r6 r7 r8 rz2 220 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 p1 p2 p3 p4 1 2 3 4 gnd va m p p4 ptmica04 p1 p2 p3 p4 1 2 3 4 gnd vdl vclk/ v_xtal ext_vref p21 ptmica04 p1 p2 p3 p4 1 2 3 4 gnd av d d (vcc) gnd drvdd p22 ptmica04 e20 vdl e7 drvdd couta cout r9 coutab coutb r11 h4 mtholes h3 mtholes h2 mtholes h2 mtholes gnd u3 3 74lvc86 clklata r33 100 couta r10 100 e35 e34 vcc gnd e33 1 2 u3 6 74lvc86 dra r34 100 couta r8 100 e32 e31 vcc gnd e30 4 5 u3 8 74lvc86 clklatb r35 100 coutab r7 100 e29 e28 vcc gnd e23 9 10 u3 11 74lvc86 drb r36 100 coutab r6 100 e22 e21 vcc gnd e16 12 13 plb gnd ground pad under part 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AD9430 u1 drvdd gnd gnd cout coutb drvdd gnd drvdd gnd drvdd gnd gnd vcc vcc gnd gnd vcc vcc gnd gnd gnd vcc vcc vcc gnd gnd gnd drvdd gnd gnd vcc gnd vcc gnd vcc vcc vcc gnd gnd gnd 00 r12 c30 10 f + c4 0.1 f vcc e36 gnd e14 gnd r5 50 j1 gnd r1 50 j2 j4 analog 1 5 3 4 2 6 pri sec r16 50 c6 0.1 f t1 adt1-1wt c7 0.1 f gnd e19 r14 29 r13 25 c3 0.1 f c2 10pf gnd 1 5 3 4 2 6 pri sec t2 adt1-1wt r13, r14 optional c47 0.1 f c11 0.1 f gnd c43 0.1 f r41 25 r42 25 c12 20pf gnd t2 optional gnd c13 20pf e1 e3 vcc e2 gnd clke clk+ gnd vcc gnd gnd vcc vcc gnd gnd vcc vcc gnd gnd gnd vcc e11 e13 vcc e12 gnd e8 e10 vcc e9 gnd r40 1k gnd e4 e6 vcc e5 gnd r39 1k gnd c1 0.1 f gnd e27 e26 vcc e24 ext_vref e29 r4 r3 gnd r2 3.9k gnd e17 e19 vcc e18 gnd r3, r4 optional data sync r1 not placed c10 0.1 f c9 0.1 f figure 18a. evaluation board schematic
rev. 0 AD9430 ?22? 87 65 12 34 opin b opin b gnd gnd ine oute gnd gnd optional amp AD9430 opin opin in+ out+ enbl v cc gnd va m p u10 + + + v cc gnd vdl gnd drvdd gnd c64 10 f c16 0.1 f c17 0.1 f c19 0.1 f c21 0.1 f c20 0.1 f c23 0.1 f c22 0.1 f c25 0.1 f c24 0.1 f c27 0.1 f c26 0.1 f c29 0.1 f c28 0.1 f c31 0.1 f c32 0.1 f c35 0.1 f c67 10 f c44 0.1 f c42 0.1 f c41 0.1 f c15 0.1 f c37 0.1 f c65 10 f c61 0.1 f c62 0.1 f c60 0.1 f c59 0.1 f c58 0.1 f c66 10 f c14 0.01 f c63 10 f + c49 10 f c48 0.1 f + vclk gnd vref gnd va m p gnd r23 100 gnd gnd r15 100 r38 100 1 2 3 e/d nc gnd u8 v cc output b output 6 5 4 vclk vclk gnd r21 100 r22 100 vclk gnd p1 p2 r38 for vf561 crystal r24 100 optional xtal rz12 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 rz10 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 r8 r7 r6 r5 r4 r3 r2 r1 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 dy b dya dy 0 dy 1 dy 2 dy 3 dy 4 dy 5 dy 6 dy 7 dy 8 dy 9 dy 1 0 dy 1 1 gnd vol c39 0.1 f gnd dx11 dx10 dx9 dx8 dx7 dx6 dx5 dx4 rz9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r1 r2 r3 r4 r5 r6 r7 r8 22 dx3 dx2 dx1 dx0 dxa dxb rz11 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r1 r2 r3 r4 r5 r6 r7 r8 22 1 2 3 4 5 6 11 12 9 10 7 8 vol c46 0.1 f gnd c45 0.1 f gnd gnd vol gnd gnd vol gnd gnd r44 1k e4z e40 e41 e39 e37 e38 r45 1k 37 38 39 40 41 42 43 44 45 46 47 48 gnd c33 0.1 f r26 2k c34 0.1 f gnd vol gnd r25 50 gnd r28 50 gnd r30 0 vol gnd c38 0.1 f gnd j3 j6 r37 0 gnd r43 1k r31 1k r32 1k gnd vol dra c40 0.1 f ad9753 r8 r7 r6 r5 r4 r3 r2 r1 r29 392 22 22 c18 1 f c14 0.1 f gnd figure 18b. evaluation board schematic
rev. 0 AD9430 ?23? figure 19. pcb top side silkscreen figure 20. pcb top side copper figure 21. pcb ground layer figure 22. pcb split power plane figure 23. pcb bottom side copper figure 24. pcb bottom side silkscreen
rev. 0 ?24? c02607?0-5/02(0) printed in u.s.a. AD9430 outline dimensions dimensions shown in millimeters and (inches) 100-lead tqfp (with exposed heat sink) (tqfp-100) 7 0 0.27 (0.0106) 0.22 (0.0087) 0.17 (0.0067) 0.50 (0.0197) bsc 1.05 (0.0413) 1.00 (0.0394) 0.95 (0.0374) top view (pins down) 1 25 26 49 76 100 75 50 14.00 (0.5511) sq 16.00 (0.6299) sq 0.75 (0.0295) 0.60 (0.0236) 0.45 (0.0177) seating plane 1.20 (0.0472) max 0.15 (0.0059) 0.05 (0.0020) bottom view 1 25 26 49 76 100 75 50 conductive heat sink 6.50 (0.2559) nom notes 1. center figures are typical unless otherwise noted. 2. the AD9430 has a conductive heat slug to help dissipate heat and ensure reliable operation of the device over the full industrial temperature range. the slug is exposed on the bottom of the package and electrically connected to chip ground. it is recommended that no pcb signal traces or vias be located under the package that could come in contact with the conductive slug. attaching the slug to a ground plane will reduce the junction temperature of the device which may be beneficial in high temperature environments. controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design

▲Up To Search▲

Price & Availability of AD9430

	To Download AD9430 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .